1. Field of the Invention
This invention relates to a liquid crystal display device. More particularly, this invention relates to a liquid crystal display device that simplifies a wiring structure of a flexible printed substrate for supplying driving signals to a driver IC mounted by a flip chip mounting system and reduces a cost by employing a novel signal transmission system.
2. Description of the Related Art
Liquid crystal display devices have been wide spread as a display device for various image displaying apparatuses. An active matrix type liquid crystal display device, that has an active cell such as a thin film transistor TFT for each pixel and switches and drives the active cell, applies a liquid crystal driving voltage (gray scale voltage) to a pixel electrode through the active cell. Therefore, this liquid crystal display device is free from cross-talk between the pixels and can conduct multiple gray scale display without employing a specific driving method for preventing cross-talk that has been necessary in a simple matrix type liquid crystal display device.
FIG. 42 of the accompanying drawings is a block diagram useful for explaining a structural example of a driving circuit in an active matrix type liquid crystal display device. FIGS. 43A, 43B, 44A and 44B are explanatory views (signal time charts) for explaining horizontal direction timing and vertical direction timing of display control in FIG. 42.
As shown in FIG. 42, the liquid crystal display device includes an interface substrate (a rigid printed substrate) having mounted thereto an interface circuit that receives display data (which will be called also xe2x80x9cpixel dataxe2x80x9d) and a control signal from a host computer, and applies pixel data, various clock signals and various driving voltages to a liquid crystal panel TFT-LCD.
The interface circuit has a display control device equipped with a timing converter TCON and a power supply circuit. The display control device outputs timing signals such as a data bus for transmitting image data, a data bus for transferring a second pixel, a clock D2 (CL2) required for a drain driver to acquire pixel data (which will be called merely xe2x80x9cdataxe2x80x9d, too), a clock D1 (CL1) required for the drain driver to switch a liquid crystal driving signal, a frame starting direction signal for driving a gate driver and a gate clock (clock G), to the liquid crystal panel.
The power supply circuit includes a positive gray scale voltage generating circuit, a negative gray scale voltage generating circuit, a voltage generating circuit for counter electrodes and a voltage generating circuit for gate electrodes.
The number of display pixels of the liquid crystal panel constituting the liquid crystal display device shown in FIG. 42 is (1,024xc3x973 in a lateral direction)xc3x97(768 in a longitudinal direction). A liquid crystal panel having higher resolution is known, too. The interface substrate for receiving the display data and the control signals from the host computer receives data in pixel unit, that is, data of each of red (R), green (G) and blue (b) as a set, and transfers (or transmits) one pixel data set in a unit time to the drain driver through data lines shown in FIG. 38.
The host computer transmits a clock signal as the reference of the unit time to the liquid crystal display device. More concretely, the liquid crystal display device having 1,024xc3x97768 pixels of this structural example uses ordinarily a frequency of 65 MHz.
The liquid crystal panel TFT-LCD has a construction such that the drain drivers (called also xe2x80x9cTFT driversxe2x80x9d) are situated in the lateral direction with the display screen as the reference. The drain drivers are connected to the drain lines of the thin film transistors TFT to supply a voltage for driving the liquid crystal. The gate drivers are connected to the gate lines, and a voltage is supplied to the gates of the thin film transistors TFT for a certain predetermined time (one horizontal operation time).
A timing converter comprises a semiconductor integrated circuit (LSI), receives the display data and the control signals from the host computer and outputs necessary display data and operation clocks to the gate drivers on the basis of them. Incidentally, the data line for one pixel has 18 bits (six bits for each of R, G and B).
The host computer transmits signals to the timing converter of the liquid crystal display device by low voltage amplification differential signals, or so-called xe2x80x9cLVDSxe2x80x9d. The timing converter transmits the signals at a CMOS level to the drain drivers. However, it is difficult in this case to supply 65 MHz pixel clocks. Therefore, the display date is transmitted in synchronism with both edges of the rise and fall of a 32.5 MHz clock.
As shown in FIGS. 43A, 43B, 44A and 44B, pulses of one horizontal time cycle are given to the gate drivers on the basis of the horizontal synchronizing (sync) signal and the display timing signal so as to supply voltages to the gate lines of the thin film transistors TFT in each horizontal time. The frame starting direction signal is given, too, on the basis of the vertical sync signal so that display can be made from the first line in one frame time unit.
The positive gray scale voltage generating circuit and the negative gray scale voltage generating circuit of the power supply circuit generate a reference voltage for converting a voltage, that is to be given to the liquid crystal in every certain time, to an alternating current. This alteration is conducted in practice as the positive gray scale voltage and the negative gray scale voltage are alternately switched and used inside the drain driver. Incidentally, the term xe2x80x9calterationxe2x80x9d used hereby means alternation of the voltage to be given to the drain driver to the positive voltage side/negative voltage side in every predetermined time. Here, the cycle of this alteration corresponds to one frame time unit.
The flip chip system described above is also called an xe2x80x9cFCA systemxe2x80x9d. This FCA system is the one that directly mounts the driving IC (drain drivers and gate drivers) to the outer periphery of one of the substrates of the liquid crystal panel (generally, the lower substrate), and is also called a xe2x80x9cchip-on-glass system (COG)xe2x80x9d. Various signals and an operation power source to the driving IC (drain drivers and gate drivers) directly mounted to the substrate of the liquid crystal panel are supplied through the flexible printed substrate FPC connected to the interface substrate.
FIG. 45 is an explanatory of a mounting example of a drain driver and a gate driver of a liquid crystal display device and an interface substrate. A drain line side flexible printed substrate FPC2 is fitted to one of the edges (to the lower edge in the drawing, a side in a major direction) of a liquid crystal panel PNL formed by bonding a lower substrate SUB1 and an upper substrate SUB2, and is folded to the back of the liquid crystal panel PNL along the arrangement of an open portion HOP.
A gate line side flexible printed substrate FPC1 is fitted to the left edge (the left edge in the drawing, or a side in a minor direction), and its connector CT3, a connector CTR3 of the interface substrate PCB and a connector CTR4 connected to a connector CT4 of the drain line side flexible printed substrate FPC2 are coupled with one another. An interface connector CT1 for connecting signals from the host computer, a timing converter TCON, and so forth, are further fitted to this substrate FPC1. Incidentally, this example employs the data transfer system of an LVDS system. A reception side signal converter (LVDS-R) necessary in this case is integrated with the same chip as that of the timing converter TCON to reduce the mounting area on the interface substrate.
An upper polarizer POL1 is bonded to the surface side of the liquid crystal panel PNL (to the surface of the upper substrate SUB2) and a display area AR is formed inside the upper polarizer POL1.
The chip IC2 mounted to the outer edge of the lower side of the lower substrate is the drain driver and the chip IC1 mounted to the outer edge of the left side is the gate driver. Symbol FGP represents a frame ground pad and FHL does a positioning hole.
In the conventional liquid crystal display device of this IPS system, the display control device equipped with the timing converter TCON supplies in parallel the date for display, the gray scale voltage (analog signals) and the pixel clocks to each drain driver. It is necessary to pass a large number of lines through the drain line side flexible printed substrate FPC2 (drain FPC) for supplying various clock signals (timing signals) inclusive of the data, the gray scale voltage and the pixel clock signal to the drain driver. Therefore, it is necessary to use either a multi-layered FPC having a narrow (thin) width or an FPC a of dual-sided wiring type having a wide (thick) width. In either case, the cost is extremely high.
Japanese Patent Laid-Open Publication No. 6-13724 proposes a construction that supplies the data and the pixel clocks to the driving IC without using the FPC. According to this reference, the drain drivers are mounted by the FCA system, and are connected in series with one another through a pass line formed by transferring a patterned metal film onto the substrate of the liquid crystal panel (serial series supply system, or so-called xe2x80x9cbucket relay systemxe2x80x9d). The term xe2x80x9cbucket relay systemxe2x80x9d is used because the signal transform for serially transferring the signals through a plurality of driving ICs is analogous to the transfer form when a plurality of people hand over and transfer serially the buckets carrying water.
Such a bucket relay system for supplying the data, the gray scale voltage and various clock signals inclusive of the pixel clock can obtain desired effects in a so-called xe2x80x9csimple matrix type liquid crystal display devicexe2x80x9d that has a relatively small number of lines.
In contrast, in the thin film transistor type liquid crystal display device, a large number of signals and voltages such as the data, the gray scale voltage, the timing signals inclusive of the pixel clock, the power supply, and so forth, must be supplied to the drain drivers. To pattern all these signals and voltages to the side edge of the liquid crystal panel, the periphery of the panel must have a large area, and so-called xe2x80x9cnarrowing of framexe2x80x9d becomes extremely difficult. This problem becomes all the more remarkable when resolution (fineness) of the liquid crystal device becomes higher.
When a plurality of drain drivers are connected in series (the bucket relay system described above), the delay amount varies depending on the difference of the wiring resistance of each of the signal lines and voltage lines and the timing margin cannot be satisfied with the result that the drain drivers fail to normally acquire the data and invite abnormal display. This is one of the problems to be solved.
The frequency of the pixel clock necessary for the drain drivers to acquire the data becomes higher as fineness of display becomes higher and electromagnetic interference (EMI) to outside is more likely to occur.
The problem resulting from high fineness similarly occurs on the gate driver side.
It is an object of the present invention to provide a liquid crystal display device that solves the problems of the prior art technologies described above and can display high-quality images at a low cost.
This and other objects and novel features of the present invention will become more apparent from the following detail description of the invention in connection with the accompanying drawings.
To accomplish these objects, the present invention is characterized in that power supply lines among lines for data signals (image or display data, timing signals for pixel clocks and gray scale voltage) are wired mainly on a flexible printed substrate FPC, and other signals and all or almost all the voltages are transferred through lines directly formed on a substrate of a liquid crystal panel.
As disclosed in Japanese Patent Laid-Open Publication No. 6-13724 described above, the wiring resistance on the substrate of the liquid crystal panel remains high when a plurality of driving ICs are merely connected by the bucket relay system in the thin film transistor TFT system, and the device sometimes fails to operate normally.
To solve such problems of the prior art, a liquid crystal display device according to the present invention includes a liquid crystal panel having pixels each being arranged at an intersection between each of a plurality of drain lines and each of a plurality of gate lines intersecting the drain lines, a plurality of drain drivers arranged in an extending direction of the gate lines, for applying gray scale voltage signals to the pixels so arranged as to correspond to predetermined groups of a plurality of drain lines on the basis of display data signals, a plurality of gate drivers arranged in an extending direction of the drain lines, for applying scanning voltage signals to the pixels arranged along the drain lines, a timing converter for generating the display data signals and various high-speed and low-speed clock signals inclusive of pixel clocks on the basis of a display signal and a timing signal inputted from outside, lines for serially transferring in series the display data signal, the gray scale voltage signal and the various high-speed and low-speed clock signals inclusive of the pixel clock to at least the drain driver mounted directly to one of the substrates of the liquid crystal panel and between the drain drivers, and gate circuits controlled by the pixel clock signals, and disposed for each of the drain drivers on either one, of both, of the input side and the output side of the display data and said gray scale voltage to the drain drivers.
This construction can avoid degradation of image quality that would otherwise occur as the delay amount varies depending on the wiring resistance of each of the signal line and the voltage line, the timing margin cannot be satisfied and the drain drivers cannot normally acquire the data.
The present invention employs the following constructions as means for solving the problems of the prior art technologies.
(1) Gate circuits are disposed on the output side of the display data signals of the drain driver and on the output side of the pixel clock signals. The gate circuit inhibits the transfer of the display data signal and the pixel clock signal to the display data line and to the pixel clock line of a following stage while the drain driver itself acquires the display data signal, and starts transferring the display data and the pixel clock signal to the following stage when the drain driver finishes acquiring the display data signal.
The gate circuit described above can appropriately use a flip-flop circuit, but can also use other means having similar functions.
(2) A timing converter is mounted to one of the substrates of the liquid crystal panel. The substrate to which the timing converter is mounted is suitably a so-called xe2x80x9cthin film transistor substratexe2x80x9d.
This construction can shorten the wiring length from the timing converter to the drain driver and the gate driver, and can simplify the construction on the side of the flexible printed substrate for supplying the signals and power when the lines for the timing converter, the drain driver and the gate driver are directly formed on the substrate.
(3) A buffer amplifier for driving a gray scale voltage dividing circuit inside the drain driver is disposed at the gray scale voltage input of the drain driver.
(4) The line width of the lines for the display data signal and the pixel clock signal as the high-speed digital signals, the line width of the lock signals as the low-speed digital signal other than the pixel clock signal and the line width of the line for the gray scale voltage as the low-speed analog signal are changed in accordance with their allowable resistance values.
(5) The wiring resistance of the line for the display data signal is set to an equal value of the wiring resistance of the line for the pixel clock signal, and the size of the terminal to be formed on the line, for connecting the drain driver is different between the high-speed digital signal line and the low-speed analog line.
The resistance values of the lines can be set to desired values in accordance with the kind of the signals, and the signal delay in the serial series transfer system can be avoided.
(6) The drain driver connection terminals for the high-speed digital signals are arranged zigzag on the minor side of the drain driver, and this arrangement of the connection terminals on one of the minor sides of the drain driver is moved as such in parallel to the other minor side so as to align the wiring resistance on both sides.
(7) The drain driver connection terminals for the low-speed digital signals and for the analog signals are arranged on the major side of the drain driver.
(8) The output terminals of the drain driver are arranged on the major side on the outer edge side of the substrate of the drain driver, and are connected to common lines formed outside a substrate cutting line from the output terminals.
(9) The drain driver power supply terminals are arranged in two rows to reduce the contact resistance.
(10) Bumps to be connected to the lines of the drain driver of a preceding stage arranged inside the substrate of the drain driver and the bumps to be connected to the lines of the drain driver of a following stage are formed in two rows in a direction parallel to the minor sides of the drain driver so that they can be used in common for two kinds of drain drivers having mutually different size specifications in the direction parallel to the minor sides of the drain drivers.
(11) The terminals of the power supply FPC of the drain driver to be connected to the lines of the flexible printed substrate are serially disposed zigzag along the outer edge of the substrate on the side of the substrate cutting line.
(12) The liquid crystal display device includes a flexible printed substrate having power supply lines and grounding lines formed thereon for supplying power to the drain drivers, and this flexible printed substrate is disposed on only the drain driver mounting surface of one of the substrates of the liquid crystal panel with the exception of the portion at which the flexible printed substrate is connected to an external printed substrate.
(13) The flexible printed substrate has a protruding portion that protrudes into the arrangement gap between the drain drivers, and an electronic component is mounted to this protruding portion.
(14) The edge of the FPC is allowed to slightly protrude from the edge of one of the substrates of the liquid crystal panel. According to this arrangement, it is possible to prevent the liquid crystal panel from directly striking a cassette or a tray during the production process and from being damaged, or to prevent static electricity from entering the drain lines.
In the construction according to the prior art, the various signals and power that are necessary for display such as the data signals (data, gray scale voltage, clock signals) are supplied to the drain drivers (inclusive of the gate drivers; hereinafter called merely the xe2x80x9cdriversxe2x80x9d, too) mounted to one of the substrates of the liquid crystal panel through the flexible printed substrate. In contrast, in the construction according to the present invention, the lines for supplying the data signals (data, clock signals, gray scale voltage) other than power among the various signals and power described above are directly formed on one of the substrates of the liquid crystal panel, and the flexible printed substrate FPC is mainly used for supplying power as can be clearly understood from the construction described above.
The lines of the data signals and the power supply lines on the gate driver side are directly formed on the lower substrate. Therefore, the flexible printed substrate can be used for only supplying power on the drain driver side. It is thus possible to reduce the number of components and to facilitate the assembly work.
To supply the data signals and power to the gate driver side, a small flexible printed substrate sheet for only the connection with the flexible printed substrate on the drain driver side or with the interface substrate is fitted to the drain driver side or, if necessary, to the gate driver side. In this way, the size of the flexible printed substrate on the gate driver side can be substantially reduced.
The lines on the substrate of the liquid crystal panel are so arranged as to connect the drivers adjacent to one another, and the clocks, the data and the gray scale voltages are transferred in each driver to the drivers of the following stages by the bucket relay system.
If this connection is made merely through the drivers, the resistances of the lines formed on the substrate are so high that the liquid crystal display device fails to operate normally. In each of the constructions described above, therefore, the present invention drives the liquid crystal display device in the ways listed below.
1) A buffer is disposed inside the driver for the digital signals such as clock and data signals, and each signal is sent to the following stage after it is buffered.
2) The signal waveforms to the drivers of the following stage are selected so that the time constant xcfx84 of the signal line satisfies substantially the equation xcfx84=(tcyclexe2x88x92tsetxe2x88x92thold)/2 to make the waveform appropriately dull. Symbols tcycle, tsetup and thold will be explained later.
3) If the buffers are merely disposed, the variance of the delay time inside the driver accumulates before each signal reaches the rearmost drain driver, in particular, among the drivers that are connected by the bucket system or in a row with the result that a sufficient timing margin cannot be secured in some cases. Therefore, a flip-flop acquires the data for each driver, and the data is sent to the driver of the following stage after timing is aligned.
4) To lower the operation frequency of the clock, the present invention employs a so-called xe2x80x9cdual edge operationxe2x80x9d that acquires the data in synchronism with both rise and fall edges of the clock.
5) In the case of the dual edge operation, the change timing of the data when the data is outputted to the driver of the following stage must be generated inside the driver. Therefore, this change timing is generated as the delay is generated in the clock inside the driver, the setup/hold time necessary for the next driver to acquire the data is secured.
6) Another method for securing the setup/hold time of the driver of the following stage is to change the resistance of the lines between the drivers by means of the clock and the data. When the wiring resistance of the clock is increased to make the waveform greatly dull, the wiring delay becomes great, and timing margin of the driver of the following stage can be secured as much.
7) Still another method of securing the setup/hold time renders the drivers operable even when the setup time of the driver of the following stage is below 0. According to this method, the normal operation can be insured even when the change timing of the data and the clock is simultaneous.
8) Still another method generates the change timing of the data and the clock to the driver of the following stage by using two-phase clocks the phase of which are different by 90 degrees.
9) When the two-phase clocks are used, the date is divided into two groups and two clocks acquire the halves of the data, respectively. In this way, the number of simultaneous switching of the data can be decreased to the half and the noise to the power supply can be reduced. In consequence, EMI can be reduced.
10) In the system described above, each driver first acquires the input data into the internal registers of its own and does not output the data to the driver of the following stage until its registers become full. In this way, useless signal transmission can be omitted, and reduction of both power consumption and EMI can be achieved.
11) In the construction 10) described above, the data must pass through the bucket relay of the number of drivers to reach the object driver after the data to the rearmost driver is outputted from TCON. Therefore, TCON must keep outputting the clocks of the number corresponding to (number of clocks necessary for bucket-relaying one driverxc3x97number of drivers) after the final data is transmitted.
12) When TCON is mounted by so-called xe2x80x9cbare chip mountingxe2x80x9d to one of the substrates of the liquid crystal panel in the same was as the driver IC, the mounting area of the peripheral circuits can be reduced advantageously.
13) When TCON is of the LVDS receiver integration type in this instance, the number of input terminals of TCON (=one of the substrates: number of terminals for connecting the lines on the TFT substrate to the external printed substrate) can be drastically reduced, and mounting becomes easier. This is more advantageous for reducing the mounting area of the peripheral circuit.
14) When TCON is mounted by bare chip mounting to the TFT substrate, the mounting position is rationally the corner at which the side having the drain drivers mounted thereto crosses the side having the gate drivers mounted thereto. According to this arrangement, the signal lines can be wired (on the TFT substrate) to both drain and gate drivers in the shortest distance.
15) The bucket relay system among the drivers is also employed also for the gray scale voltage lines as the analog lines. A current, though limited, generally flows from the gray scale voltage input to the DAC section inside the driver in both R-DAC system and C-DAC system. Since the wiring pattern on the liquid crystal panel has a relatively high resistance, this weak current is likely to cause the shift of the gray scale voltage supplied to the driver, and display quality drops.
To prevent this problem, the current flowing through the gray scale voltage input terminals must be lowered to a level that does not render any problem. It is effective for this purpose to dispose a buffer (operational amplifier) at the gray scale voltage input.
16) It is effective from the aspect of efficiency to arrange the terminals for connecting the drivers on the minor side of the driver chip that has not been dealt with as the input terminals. When the input terminals cannot be arranged fully on the minor side, the major side may be used, too.
17) The drain lines and the gate lines inside the liquid crystal panel are short-circuited with one another by common lines (short-circuit lines) to prevent the shift of performance due to static electricity during the production process. The common lines are cut off before the product is completed. In the conventional devices, the common lines are situated below the body of the driver chip and are cut off by means such as laser.
When the lines are extended outside the outer shape of the product of the liquid crystal panel while passing below the body of the driver chip, the common lines can be disposed at a cutting/removing portion outside the product. In this case, the common lines can be cut off simultaneously with the cutting process of the substrate (lower substrate: glass) of the liquid crystal panel. In consequence, the conventional cutting process by using laser can be omitted, and the production cost can be lowered.
18) When the lines for the clock, data and gray scale voltage are wired on the lower substrate (TFT substrate), it is fundamentally only the power supply lines that must be wired on the flexible printed substrate. In any case, the number of lines is only a few. Therefore, even when the flexible printed substrate FPC is not folded to the back of the liquid crystal panel as has been necessary in the conventional system, the required portion is only the width of the compression-bonding portion to the liquid crystal panel. In this case, the construction can be simplified and the outer dimension of the liquid crystal display device can be reduced. Because the assembly work can be simplified, the cost of production can be reduced.
19) In the case 18) described above, when the back of the compression-bonding portion of the flexible printed substrate FPC to the liquid crystal panel is utilized for wiring, design of the flexible printed substrate FPC becomes easier and the cost can be lowered.
20) The flexible printed substrate described above basically has a straight shape (simple straight shape) the width of which is only the width of the compression-bonding portion, but a small number of electronic components such as a chip capacitor must be mounted in many cases to this portion. In this case, the electronic components become the obstacle for compression-bonding of FPC. Therefore, the flexible printed substrate FBC is provided with a portion that protrudes into the arrangement gap between the drivers, and the electronic components can be mounted to this protruding portion without any problem.
Furthermore, the present invention omits the flexible printed substrate FPC, that has been used in the past on the gate side, by forming the data lines and the power supply lines on the gate driver side into a substrate shape. The present invention thus decreases the number of components and simplifies the assembly work. The present invention uses a single-layered flexible printed substrate FPC having only the power supply lines as FPC on the drain driver side, and thus simplifies the construction of the drain driver side FPC. Consequently, the present invention can reduce the number of components and the number of process steps of the liquid crystal display device, and can reduce the cost of production.
The liquid crystal display device according to the present invention mentioned above, should be characterized as follows also. One of examples of the liquid crystal display device is described as a liquid crystal display device comprising, (A) a liquid crystal panel having a pair of substrates, between which a liquid crystal layer is interposed, one of the pair of substrates has a plurality of gate lines extending in a first direction, a plurality of drain lines extending in a second direction transverse to the first direction, and a plurality of pixels being arranged along the first and second directions (in a matrix manner), each of the plurality of pixels has a switching element (or, an active element), (B) a plurality of drain drivers being juxtaposed along the first direction and applying gray scale voltage signals to the switching elements of the plurality of pixels in accordance with display data signals, respectively, (C) a plurality of gate drivers being juxtaposed along the second direction and controlling the switching element, and (D) wiring lines formed on the one of the pair of substrates, respective ones of which supply at least the display data signals and a clock signal to a first one of the plurality of drain drivers arranged at one end of the one of the pair of substrates and transfer the display data signals and the clock signal between the plurality of drain drivers in order from the first one of the plurality of drain drivers, wherein (E) at least one of the plurality of drain drivers has at least one gate circuit being controlled by the clock signal, by which the display data signals and the clock signal are switched either (I) to be acquired by xe2x80x9cthe at least one of the plurality of drain driversxe2x80x9d or (II) to be transferred to xe2x80x9canother of the plurality of drain driversxe2x80x9d being arranged adjacent to the at least one of the plurality of drain drivers. Moreover, in accordance with the same basis mentioned previously, (F) this liquid crystal display device may further comprise a timing converter receiving display data and a timing signal from an external circuit to the liquid crystal display device and generating the display data signals and the clock signal in accordance with the display data and the timing signal, (G) the at least one gate circuit may be provided for each of the plurality of the drain drivers, or (H) the at least one gate circuit may be arranged at least one of an input portion and an output portion of the display data signals and the clock signal provided in the at least one of the plurality of drain drivers in this liquid crystal display device.
Though the typical construction and operations of the present invention have thus been described, other constructions and operations of the present invention will be explained in detail in later-appearing embodiments.
These and other objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings.